1. Technical Field
The present disclosure relates to methods of creating photo mask layouts and mask imaging systems, and more particularly, to methods and systems of creating photo mask layouts including optical proximity correction (OPC) patterns.
2. Discussion of Related Art
The scaling down of large scale integrated circuits. (LSIs) has been accelerated due to the development of photolithography technology. Photolithography is a process used in micro-fabrication to selectively remove parts of a thin film (or the bulk of a substrate). It uses light to transfer a geometric pattern from a photo mask to a light-sensitive chemical (photoresist, or simply “resist”) on the substrate. A series of chemical treatments then engraves the exposure pattern into the material underneath the photoresist. The scale of LSIs has been reduced to 90 nm, 65 nm, 45 nm and lower to meet the ever more stringent design rules for manufacturing semiconductor devices. Therefore, the size of a pattern transferred onto a wafer is substantially smaller than a wavelength of an exposure beam used in the photolithography process, generating an optical proximity effect caused by optical diffraction and interference. However, the resulting optical proximity effect can limit photolithography resolution.
Optical proximity correction (OPC) is a photolithography enhancement technique commonly used to compensate for image errors due to the optical proximity effect. One conventional OPC technique enhances a contrast and sharpness of a main pattern of a photo mask projected on a wafer by adding a sub-resolution assist features (SRAF) pattern to the photo mask.
The number and size of SRAF patterns may be determined according to the size of main patterns and the space between them. A reduction of design rules leads to a reduction in the size and space of the main patterns, which continuously reduces the size of the SRAF pattern. However, it can be difficult to secure a reliable photolithographic process for the reduced SRAF pattern.
FIG. 1 illustrates microscopic images of defects in various SRAF patterns on a photo mask 10 obtained by a conventional photo mask manufacturing process. Referring to FIG. 1, 4 images around the photo mask image 10 are partially enlarged images of respective rectangular areas A through D of the photo mask image 10. The photo mask image 10 is manufactured with the SRAF patterns to fabricate a semiconductor device having a substantial critical dimension (CD) of 45 nm. Missing defects in an SRAF pattern are generated in the area A, bleak defects in an SRAF pattern are generated in the area B, and thinning defects in an SRAF pattern are generated in the area C. No defect in an SRAF pattern is generated in the area D. These defects may be distributed in a circularly scattered pattern σ with various defect types and densities caused by loading errors that frequently occur during the conventional photo mask manufacturing process. The defects in SRAF patterns cause defects at the wafer level, such as collapsing of main patterns to be transferred onto substantial wafers or unwanted transferring of an SRAF pattern onto a wafer.
Thus, there is a need for methods and systems of generating photo mask layouts that can prevent or reduce defects in an SRAF pattern.